FreeCAD: master 9a702d20

Author Committer Branch Timestamp Parent
Jriegel Jriegel master 2014-01-08 19:36:39 master 7cf3b61c
Changeset some fixes
add - src/Mod/Import/App/SCL/Aufspannung.stp Diff File
mod - src/Mod/Import/App/SCL/Part21.py Diff File
mod - src/Mod/Import/App/SCL/SimpleReader.py Diff File